|標題:||Solving the Scaling Issue of Increasing Forming Voltage in Resistive Random Access Memory Using High-k Spacer Structure|
Sze, Simon M.
Department of Electronics Engineering and Institute of Electronics
|關鍵字:||device scaling;forming voltage;resistive random access memory (RRAM);spacer structures|
|摘要:||In this study, the rising forming voltage issue during device cell scale-down in resistance random access memory (RRAM) is solved by introducing new high-permittivity (high-k) material as the side-wall spacer structure, unlike the normally used low-permittivity (low-k) material. Simulated electrical fields based on COMSOL Multiphysics software results suggest a RRAM device with a high-k spacer effectively confines the electric field. The effects of this confined electric field are notable, especially when the device cell is scaled down. The device fabrication process is modified to incorporate the high-k sidewall. Cross-sectional transmission electron microscopy imaging confirms the existence of SiO2 and HfO2 as the spacer structures in two different devices. Electrical measurements of forming voltages ranging from 1 to 0.16 mu m(2) are conducted to verify the effects. Statistical measurements confirm that the forming voltages of the devices with high-k material as sidewall do not increase with a reduction in device cell size. Moreover, reliability tests, including endurance and retention for the high-k sidewall device, also exhibit very stable resistance switching characteristics. As a result, the structure that is proposed successfully solves the forming voltage issues within small device cells in RRAM without any cost to device reliability.|
|期刊:||ADVANCED ELECTRONIC MATERIALS|
|Appears in Collections:||Articles|