標題: 鰭狀、穿隧場效電晶體元件於超低功耗靜態隨機存取記憶體、邏輯電路及類比電路應用之設計與分析
Design and Analysis of Nanoscale FinFET and Tunnel FET Devices for Ultra-Low-Power SRAM, Logic and Analog Applications
作者: 陳盈年
莊景德
Chen, Yin-Nien
Chuang, Ching-Te
電子工程學系 電子研究所
關鍵字: 鰭狀場效電晶體;穿隧場效電晶體;變異度;邏輯電路;類比電路;靜態隨機存取記憶體;FinFET;TFET;Variability;Logic Circuits;Analog Circuits;SRAM cells
公開日期: 2016
摘要: 本論文旨在針對微縮鰭狀場效電晶體及穿隧場效電晶體於超低功耗靜態隨機存取記憶體、邏輯電路及類比電路應用提供一完整的評估與分析。在此論文中,我們考慮元件與電路間的相互影響(interaction)以及共同之最佳化(co-optimization)以全面性的呈現上述微縮鰭狀場效電晶體及穿隧場效電晶體在元件/電路層面的潛力與隱憂。藉由本研究,我們探討元件特性和低電壓操作對於邏輯電路(logic circuits)的漏電/延遲,靜態隨機存取記憶體(SRAM)的穩定度/效能以及類比電路的功耗/效能及其他重要考量因素的影響,進而提供在此篇論文裡我們所提出的電路設計以及未來電電壓操作電路設計的方向。 擁有優異的靜電完整性(electrostatic integrity)以及對於不均勻摻雜擾動(random dopant fluctuation)的免疫,鰭狀場效電晶體是取代傳統平面式金氧半場效電晶體最有競爭性的元件。於此同時,其可獨立閘極操作(independent-gate control)的元件架構有助於優化元件特性或是電路功能。我們全面性地檢視傳統6T transistor記憶體單元,獨立閘極控制Column-Decoupled的6T記憶體單元以及我們所提出的獨立閘極控制7T記憶體單元在穩定度以及效能上的表現。經由本研究我們發現,我們所提出的獨立閘極控制7T記憶體單元由於其使用了獨立閘極控制的元件於分隔讀取與寫入路徑的讀取電晶體(reading transistor)上,同時亦使用在兩個存取控制電晶體(access transistor)上形成cross-point的架構,進而提供了適當的寫入靜態雜訊邊界(static noise margin)以及顯著的改善了讀取和半讀取(Half-select)靜態雜訊邊界。除此之外,我們探討鰭線邊緣粗糙度(fin Line-Edge-Roughness)對於上述記憶體單元在讀取穩定度以及讀取效能的影響。我們研究分析顯示使用獨立閘極控制的元件雖然會比共同閘極控制(tied-gate)變異性差,整體而言,我們提出的獨立閘極7T記憶體單元提供了最佳的讀取靜態雜訊邊界變異度(μ/σ),以及解決了另兩個記憶體單元由於漏電流變異造成之存取資料翻轉的情況,顯示了其適合應用於低操作電壓靜態隨機存取記憶體。 透過能帶間穿隧效應(band-to-band tunneling)所產生的電流,穿隧場效電晶體(TFET) 由於其擁有克服熱電子(thermionic)限制的能力以及提供更為優異的切換特性被視為在未來超低電壓操作邏輯電路應用上極具競爭力的元件。首先我們先廣泛性的分析穿隧場效電晶體的元件特性,而其元件架構造成元件本身有較大的閘極-汲極電容(CGD),在電路操作上惡化了轉換延遲以及轉換能量。因此,我們全面性的比較幾種元件設計,包含使用雙重介電材質(Dual Oxide)、汲極端遠離閘極控制區(Drain-Side Underlap) 、使用雙重金屬閘極材料(Dual Metal Work Function),對於在維持穿隧場效電晶體優異的轉換特性的同時如何優化其閘極-汲極電容作探討。我們研究分析指出使用雙重介電材質(Dual Oxide)設計可得到最佳降低閘極-汲極電容(CGD)同時保有穿隧場效電晶體優異的轉換特性。另一方面,隨著操作電壓持續的下降,若要維持傳統金氧半場效電晶體仍可應用於超高速、超低功耗的操作上的話,新穎輔助電路如使用雙重操作電壓以及雙重臨界電壓設計則是不可或缺的。因此,我們針對傳統金氧半場效電晶體、金氧半場效電晶體採用上述電路架構、傳統穿隧場效電晶體以及穿隧場效電晶體採用雙重介電材質設計來探討何者更有潛力應用於次0.2V超高速、超低功耗的電路操作上。我們分析了其在靜態邏輯電路、Bus驅動(Bus Driver)以及閂鎖(latch)上,延遲、動態能耗、待機能耗上的表現。我們分析結果顯示穿隧場效電晶體採用雙重介電材質設計更適用於次0.2V超高速、超低功耗的電路操作。 我們也針對多種穿隧場效電晶體記憶體單元以及我們所提出的兩個記憶體單元,7T穿隧場效電晶體記憶體單元還有混合穿隧場效電晶體以及金氧半場效電晶體8T記憶體單元在穩定度、效能、記憶體單元佈局面積以及使用寫入輔助電路的有效性作全面性的分析與比較。 本論文也針對穿隧場效電晶體在類比/混頻電路應用上的潛力作探討研究。由於傳輸機制不同於傳統鰭狀場效電晶體,我們從本質元件物理特性觀點出發,分析以及比較鰭狀場效電晶體以及穿隧場效電晶體的類比特性指標。我們研究分析結果發現穿隧場效電晶體由於其在低壓下較佳的轉換特性,在超低電壓/功耗的類比應用上,其可提供較佳的增益(gain)以及線性度(linearity)。鰭狀場效電晶體由於其可提供的驅動電流較佳,更適用於高效能類比電路應用上面。除此之外,我們亦針對兩種元件在運算轉導放大器(operational transconductance amplifier)上的特性指標以及頻率響應,以實際觀察兩者在類比電路應用之潛力與劣勢。我們研究結果分析指出,在超低功耗應用上,由於穿隧場效電晶體擁有較佳的本質元件增益,因此在同樣功耗的設計下,其比鰭狀場效電晶體運算轉導放大器提供了兩倍大的單位增益頻率(unit-gain frequency) 、10dB多的共模抑制比(common-mode rejection ratio)。 隨著製程微縮以及操作電壓的下降,元件本質變異(intrinsic device variation)對於元件特性的改變以及其對電路設計上是相當重要的考量因素。本論文亦涵蓋功函數變異(Work Function Variation)以及鰭線邊緣粗糙度(Fin Line-Edge-Roughness)對於鰭狀場效電晶體以及穿隧場效電晶體元件特性的影響。我們的研究指出,由於傳輸機制的不同,元件本質變異對於此二元件的影響迥異; 元件本質變異影響鰭狀場效電晶體整個傳輸通道,而對於利用能帶間穿隧效應的穿隧場效電晶體,區域化尤其是穿隧邊界的改變為元件特性影響之主要因素,而在元件本質變異的比較中,我們也發現鰭線邊緣粗糙度對於此二種元件有較大的變異度。我們亦針對功函數變異以及鰭線邊緣粗糙度對於我們所提出的混合穿隧場效電晶體與金氧半場效電晶體、金氧半場效電晶體、穿隧場效電晶體8T記憶體單元在讀取、寫入、半讀取靜態雜訊邊界作全面性的分析與比較。我們的研究指出,我們所提出的混合穿隧場效電晶體與金氧半場效電晶體8T記憶體單元,由於其操作機制的優勢,在各項靜態雜訊邊界都可以達到五個標準偏差變異度的穩定性。我們所提出的混合式8T記憶體單元對於靜態隨機存取記憶體操作於超低壓下是較佳的設計選項。
The goal of this dissertation is to provide an extensive assessment of nanoscale FinFET and TFET devices for ultra-low-power application in SRAM, logic and analog. Device-circuit interactions and co-optimizations are considered to demonstrate the advantages and concerns of these emerging devices based circuits from both the device and circuit point of view. Through our analysis, impacts of device characteristics and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAMs, on the power/performance of analog circuits are evaluated to offer insights for both our proposed innovative circuit designs and for future low-voltage circuit designs. With superior electrostatic integrity and immune to random dopant fluctuation, FinFET device serves a promising role to replace conventional bulk MOSFET device. In addition, the possible adoption of the independent-gate control facilitates FinFET device characteristics and circuit functions. We extensively examine the stability and performance of our proposed Independently-controlled-Gate (IG) 7T FinFET SRAM cell with the conventional 6T FinFET SRAM cell and IG 6T Column-Decoupled FinFET SRAM cell. Through our analysis, our proposed IG 7T FinFET SRAM cell which exploits the independently-controlled-gate (IG) FinFET devices for reading transistor to decouple read/write paths and for access transistors to form cross-point structure provides comparable Write SNM (WSNM) and significant improvement in Read SNM (RSNM) and Half-Select SNM (HSSNM). In addition, with the 3D atomistic TCAD simulator generated Fin Line-Edge-Roughness (Fin LER) pattern, the impacts of the intrinsic device variability on the cell Read stability and Read Performance are extensively investigated. The results indicate that although the variability of independently-controlled-gate device is slightly larger compared to tied-gate device, our proposed cell provides the best μ/σ in RSNM and no Read failure events happened while other two counterparts encounter severe Read failure events due to leakage current from unselected cells flipping the storage data, revealing that our proposed cell is suitable for robust low Vmin SRAM application. Utilizing band-to-band tunneling as the major transport mechanism, Tunnel FET (TFET) device with capability to surmount the thermionic limitation and to provide superior switching characteristics is regarded as the potential candidate for ultra-low voltage digital applications. Through our comprehensive analysis of the TFET device characteristics, it is found that the pronounced Miller capacitance (CGD) in TFET device undermines the steep-slope advantages and degrades both the switching delay and switching energy. The impacts of several device designs including the Dual Oxide (DOX), Drain-Side Underlap (Dund) and Dual Metal Work Function (DWF) on mitigating the Miller capacitance while maintain the switching characteristics of TFET device are comprehensively investigated and compared. Our results indicate that TFET device with DOX design provides superior reduction in Cinv and C¬gd while retaining comparable Ion-Ioff characteristics among the three design techniques. On the other hand, to enable MOSFET devices for high-speed low-power operation with extensively reduced supply voltage, advanced assist-circuit such as using the dual-supply dual-VT technique is indispensable at the cost of more complicated assist-circuits and needs of on-chip level shifter to generate dual supplies. We use TCAD mixed-mode simulations to comprehensively investigate the feasibility of sub-0.2V high-speed low-power circuits with the four topologies, nominal MOSFET-based circuits, MOSFET-based circuit with dual supply, dual-VT assisted circuits, nominal TFET-based circuits and TFET-based circuits with DOX design. The delay, dynamic energy, and Standby power of the logic circuits including NAND, Inverter, BUS Driver and Latch are comprehensively analyzed and compared. The results indicate that DOX TFET would be the best candidate in considering both the energy-delay product (EDP) and leakage power for NAND, Inverter and Latch circuits. While for Bus Driver in which the largest delay would take place among all logic blocks investigated, both the nominal and DOX TFET-based circuits outperform the nominal MOSFET-based circuits in EDP by about two orders of magnitude and consume comparable Standby power, revealing the potential of TFET device to achieve high-speed low-power circuit operation at VDD = 0.2V. In addition to logic circuits, various TFET SRAM cells including conventional 7T/8T SRAM cell, 6T SRAM cell with assisted footer and our proposed cells to circumvent the difficulties implementing TFET with conventional 6T SRAM topology are statistically examined and compared. The results indicate that our proposed 7T Drive-Less (DL) TFET SRAM cell with the utilization of 4T DL SRAM as the basis along with the independent gate control can effectively improve the stability of the bit cell in Hold, Read and Write mode with adequate bit cell area compared with other counterparts. On the other hand, with the process compatibility in TFET and CMOS device fabrication, we propose a mixed TFET-MOSFET 8T SRAM cell to exploit merits of both TFET and MOSFET devices. The detailed analysis on stability, performance and effectiveness of using different write-assist schemes are extensively demonstrated. Through our comprehensive study, our proposed mixed TFET-MOSFET 8T SRAM cell provides significant improvement in stability, performance and Vmin, exhibiting the chance to stand for robust ultra-low power SRAM design at the cost of slightly larger bit cell area. The advantages of the TFET devices for analog applications are assessed to examine the potential for SoC applications. The detailed analog properties and the figure-of-merit (FOM) of TFET and FinFET devices including the transconductance (gm), output resistance (Ro), intrinsic gain (gm x Ro), intrinsic capacitance and linearity are comprehensively studied from intrinsic device physics point of view. Our analysis indicates that for cost-performance ultra-low voltage/power applications, TFET provides substantial merits in intrinsic gain compared with the FinFET device while for high-performance applications, FinFET device outperforms the TFET device at moderate and high voltages. Besides, the operational transconductance amplifier is taken as the fundamental block to investigate the opportunities and concerns of the TFET device for analog/mixed-signal circuit applications. The results indicate that for cost-performance ultra-low power application, TFET OTA provides more than two times higher unity-gain frequency (fT), and 10dB larger common-mode rejection ratio (CMRR) than FinFET OTA at comparable power consumption design. As the continual scaling of device dimension along with the reduced supply voltages, the impacts of intrinsic device variations become the critical concerns affecting device characteristics and circuit designs. The in-depth assessment of the impacts of Work-Function Variation and Fin Line-Edge Roughness on TFET and FinFET device characteristics are carried out through atomistic 3D TCAD simulations. Look-up table based Verilog-A model calibrated with TCAD results is built for each variation source and incorporates with HSPICE simulations to efficiently investigate impacts of Work-Function Variation and Fin Line-Edge Roughness on TFET SRAMs including our proposed mixed TFET-MOSFET 8T SRAM cell, conventional FinFET 8T SRAM cell and TFET 8T SRAM cell. For the first time, the feasibility/issues of each SRAM cell for ultra-low voltage operation considering intrinsic device variability are addressed. Our results indicate that our proposed mixed cell with exploiting merits of both devices provides superior stability and insusceptibility to intrinsic device variations, revealing its viability and robustness to operate at ultra-low voltages.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT079811505
http://hdl.handle.net/11536/141840
Appears in Collections:Thesis