Title: 應用於W頻帶的65奈米互補式金氧半製程之寬頻接收機設計
Design of W-band 65nm-CMOS Wideband Receiver
Authors: 羅宇崙
Luo, Yu-Lun
Hu, Shu-I
Keywords: 鎖相迴路;低雜訊放大器;混頻器;壓控振盪器;接收機;PLL;LNA;Mixer;VCO;Receiver
Issue Date: 2017
Abstract: 近年來,由於金屬氧化物半導體(CMOS)製程技術的進步,使得製作高整合度的接收機變為可能。高整合度的接收機不僅有低成本的優點,且因體積的縮小,能夠實現高整合度的影像感測系統。然而整合的過程中也遇到許多挑戰,如晶載面積的限制以及矽基板的高損耗等等,都是值得仔細深入研究的問題。 本論文所設計的W頻帶寬頻接收機使用台積電65奈米製程,包含射頻前端電路以及產生本地振盪頻率的鎖相迴路。射頻前端電路包含低雜訊放大器、混頻器和中頻放大器。鎖相迴路以切換振盪器的方式產生兩種頻率,妥善的分配本地振盪頻率達到寬頻的表現。 論文的第一部分敘述常見接收機基本架構,第二部分詳細介紹本次設計接收機之架構,第三部分展示模擬結果和晶片佈局圖,最後總結本次設計所遇到的問題以及未來方向。 
Recently, due to the improvement of manufacturing technology of CMOS, making highly integrated receiver become possible. Highly integrated receiver is not only low-cost but also make building compact imaging system possible by the reduction of volume. Nevertheless, there must be several challenges waiting to be deal with, such as the restriction of on-chip area or lossy silicon substrate at high frequency and so on. This thesis proposed a W-band wideband receiver, which contains RF front-end circuit and the Phase-Locked loop for generating Local Oscillating (LO) frequency. The RF front-end circuit includes Low Noise Amplifier (LNA), Mixer and Intermediate frequency amplifier. PLL generate two frequency options by switching Voltage-controlled oscillator. Through proper planning of LO frequency, wideband down-conversion can be achieved. The first part of the thesis introduces several common architecture of receiver. The second thoroughly describe the proposed receiver. Then the third part demonstrates the simulated results and layout of the chip. The final part concludes the challenges I facing in designing circuit and recommendation for future work.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070350211
Appears in Collections:Thesis