Title: 在介面改質與不同製程條件下,HTO鍺鐵電電容的特性探討
Investigate the characteristic of HTO germanium ferroelectric capacitor under the interface modification and different process conditions
Authors: 范景淳
Fan, Ching-Chun
Chin, Feng-Der
Keywords: 鍺;鐵電;電容;介面改質;鍺電容;鍺鐵電電容;電容-電壓特性;Germanium;Ferroelectric;Capacitor;Interface Modification;Ge Capacitor;Germanium Ferroelectric Capacitor;C-V Characteristic
Issue Date: 2017
Abstract: 從矽積體電路發明以來,半導體製程依照摩爾定律的進程,而持續微縮閘極線寬,以求得性能、功耗、功能及成本都更加優異的晶片。隨著閘極線寬微縮到次微米以下,半導體業為了能夠做出特性更加優異的電晶體,因而發展出各種不同的材料,來取代舊有電晶體的各部分。如以更新穎的金屬矽化物取代舊有的金屬矽化物,以及源極與汲極的矽改成可以對通道施加應力的矽化碳與矽化鍺,還有用二氧化鉿等高介電係數之材料取代二氧化矽絕緣層,甚至是以金屬取代多晶矽作為閘極。同時,以半導體元素鍺作為電晶體通道的研究也日益增加。然而,鍺本身不良的介面特性,以及二氧化鍺的不穩定性,是要達成優異的鍺電晶體所要面臨的關鍵困難。 在本論文中,我們將以鍺作為研究材料,是著眼於鍺元素有著比矽元素更高的電子與電洞的遷移率的特性,是能夠做出電特性更好的電晶體。為了滿足良好與穩定的鍺介面,我們研究以三種介面改質的方法,配合各種不同的製程,如改變退火溫度及時間、不同的氧化鉿 鎵的厚度、快速熱退火的溫度等,試著去改善鍺與氧化鉿鎵的介面特性,降低其介面缺陷的密度,並阻擋二氧化鍺的擴散。讓氧化鉿鎵鍺電容,除了擁有高電容值之外,同時具有鐵電的特性。
Since the invention of silicon integration circuit, the semiconductor process have scaled down the gate length with the path of the Moore’s law to get better performance, lower power consumption, more functions and cheaper chips. With the scaling down process evolving into the sub-micron reign, in order to make characteristic of transistor more prominently, the semiconductor industry developed many kinds of material to replace the old parts of the transistor, such as silicide which changes a silicide material to a novel silicide material, strained-silicon which replaces silicon in the source/drain region with SiC or SiGe which can apply the force to the channel, and high- material, hafnium oxide for instance, to replace the silicon dioxide insulator, and metal gate to replace the poly-silicon gate. Meanwhile, it is more popular that the research of semiconductor atom, germanium, as the channel of transistor. The bad interface property of germanium and instability of germanium dioxide, however, are the key obstacles for researchers to attain the outstanding germanium transistor. In this thesis, germanium was our research material to fabricate the capacitor with better electronic characteristic because of its higher electron and hole mobility than silicon’s counterparts. To gratify well and stable germanium interface, we have executed three interface modification procedures with different processes such as changing time or temperature of post-deposition annealing, different HfTaO (HTO) thickness and rapid thermal annealing to improve the interface characteristic between germanium and HfTaO and lower the density of interface defect, and block the diffusion of GeO2. With these processes, germanium capacitor with HfTaO can have high capacitance and even ferroelectric property.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070450140
Appears in Collections:Thesis