Strain Effects on Sidewall Damascened Tri-Gate Poly-Silicon Fin-FETs
|關鍵字:||應變效應;多晶矽;鰭式電晶體;無接面電晶體;Strain effect;Poly-Silicon;FinFET;Junctionless transistor|
|摘要:||近年來隨著可攜式電子產品蓬勃發展到人手可見，然而可攜式電子產品中扮演重要關鍵角色的積體電路元件通道也持續微縮進入奈米等級尺寸，也因為元件通道持續微縮逼近物理極限所面臨到短通道效應、漏電及微影製程等問題，為了克服上述的問題在電晶體結構上必須由傳統二維平面式演進到新穎三維立體式的世代，因此三維立體鰭式場效電晶體 (Fin-FET) 在近年來被廣泛研究及討論。
在此篇論文中，我們提出新穎氮化矽/二氧化層/氮化矽 (Nitride/Oxide/Nitride) 三明治結構與側壁鑲嵌技術 (Sidewall Damascened Technique) 製作出無鄰近應變技術 (Strain Proximity Free Technique) 及應變記憶技術 (Strain Memorize Technique) 兩種不同應變效應的側壁鑲嵌三閘極多晶矽鰭式電晶體技術 (Strain Effect on Sidewall Damascened Tri-Gate Poly-Si FinFETs),利用濕式選擇性蝕刻直接蝕刻出鰭式通道, 製程中無須透過先進曝光機台製作出具備鰭式場效電晶體，在結合臨場摻雜之技術 (In-Situ Doped) 搭配製作出無接面式並具備應變效應的矽奈米鰭式場效電晶體，此種電晶體擁有良好電性特性如臨界擺幅、漏電流控制、開關電流比值及載子遷移率，具備以上優勢預期在未來閘極長度在持續微縮過程中將更具發展的潛力。|
Recently the booming of portable electronic products are part of people’s everyday live. Nevertheless, the channel dimension of integrate circuits devices aggressively shrink into nanometer-scales. The integrate circuits are participate as key component of portable electronic products. because of continuously shrink of the channel dimension which near physical limitations had induce short channel effect, leakage and require expensive lithography tools are become a serious events. The current conventional planar transistor structure has revolutionized from two-dimensional to novel three-dimensional generation. This novel three dimension architecture able to conquer aforementioned events. Accordantly the enhancement of three-dimensional architecture Fin-FET had been considered extensive in many research and discussion. In this thesis, we propose a novel nitride/oxide/nitride sandwich structure by selective etch define fin shape channel. The process using innovative sidewall damascened technique without any advance lithography tools. With this sandwich structure we can easily implement strain proximity free technique to fabricated high performance transistor. Finally employ in-situ n+ doped the junctionless fin field effect transistor with strain effect are successfully demonstrated. This junctionless transistor exhibit excellent device characteristics of low subthreshold swing, low off state leakage current, high on/off ratio and high carrier mobility. A significant performance improvement had advantage and continuously shrink of the gate length will be the promising candidate in the future.
|Appears in Collections:||Thesis|