Novel Multi-level Clock Driving Technique and Circuit-Simulation-Based Multi-objective Evolutionary Algorithm for Design Optimization of a-Si:H TFTs Gate Driver Circuits for Bio-ICT Panel Display Applications
|關鍵字:||非晶矽薄膜電晶體;閘極驅動電路;多目標演算法;最佳化;電路設計;a-Si:H TFTs;gate driver circuit;multi-objective evolutionary algorithm;optimization;circuit design|
In Information and Communication Technology (ICT), the panel display had been widely used in many applications, such as TVs, cell phones, flats, multi-parameter monitors, and ultrasound medical equipments. The structure of TFT-LCD has a backlight unit and a panel display is composed of the active matrix which has gate lines controlled by ASG driver circuits, liquid crystal (LC), the transparent electrode and the color filter (CF) film between two polarizer films. Nowadays, panel displays with various sizes are widely used. To fabricate panel displays with high performance and competitiveness, ASG driver circuits play one of key techniques. In general, ASG driver circuit designs strongly rely on adjusting and testing by experienced engineers. However, with the diverse needs for panel displays of information, communication, and biomedical science, designs of ASG driver circuits are getting more and more complex. Thus, we should consider more engineering parameters which need to be optimized at the same time. The genetic algorithm (GA) is usually used for circuit designs, which we can only write one cost function with many design specifications. However, due to many characteristics of ASG driver circuits, the adjusting of the cost function is very difficult. Recently, the multi-objective evolutionary algorithm (MOEA) which can optimize many cost functions at the same time has become more popular in circuit designs. In this study, we optimize the ASG driver circuits by using the MOEA. To improve the power consumption of panel display, we propose the multi-level clock driving method. Cooperating with display manufacturer in Taiwan, we successfully fabricate the sample of the optimized ASG driver circuit which has excellent characteristics. First, the problem of the ASG driver circuit on unified optimization framework can be seperated into two parts, the circuit problem and the solver. The configuration file of the circuit problem calls the mask file which provides the positions of masked parameters as well as the parameter file which sets the ranges of parameters. The configuration file also provides parameters to intermediate _file (written by C++ program) for optimization. The solver generates and chooses the solutions. Furthermore, it also calls the external circuit simulator to calculate the characteristics of ASG driver circuits. The terminal condition is according to generations setting by the configuration file. We design a six-stage ASG driver circuit by using optimized method based on the MOEA. Each stage of this ASG driver circuit has 17 a-Si:H TFTs and 4 capacitors. The objective specifications are the fall time < 3 s and the peak voltage of the ripple < -9 V. The fall time and the peak voltage of the ripple derived from the original design are 4.78 s and -8.81 V, respectively. After optimization, the fall time successfully decrease to 2.65 s, and the peak voltage of the ripple decrease to -9.07 V. Then, in order to reduce the power consumption, we add a novel 3-level clock driving to the optimized ASG driver circuit. The fall time further reduce to 2.35 _s and the peak voltage of the ripple reduce to -9.96 V. Overall, the fall time has about 50 % reduction. Moreover, the fall time of measured data is 2.48 s; the peak voltage of the ripple is -11.3 V. The measured data has a good agreement with the values of simulations, and the ripple of ASG driver circuit also become more smoother. In addition, stress effect would affect the stability and the lifetime of products. The factors of stress effect are temperature, the magnitude of bias voltages and the conducting time. Because of high level voltages, each TFT will suffer from the offset of the threshold voltage. Therefore, we hope the conducting time of TFT become shorter. In Chapter 4, we drive the ASG driver circuit by using three clock signals, and its duty ratio is 33%; in Chapter 5, we design a twelve-stage ASG driver circuit with four clock signals by using optimized method based on the MOEA, and successfully reduce the duty ratio to 25% which decreasing the stress effect. Each stage of the ASG driver circuit has 13 a-Si:H TFTs and 2 capacitors. The objective speci_cations are the rise time < 3.5 s, the fall time < 5.5 s, the amplitude of the ripple < 1.2 V, the total width of TFTs < 12000 m and the clock Ctotal < 25 pf. After optimization, the rise time successfully decrease from 3.63 s to 3.29 s (9% reduction), the fall time decrease from 5.96 s to 5.37 s (10% reduction), the amplitude of the ripple decrease from 1.23 V to 1.15 V (7% reduction), the total width of TFTs decrease from 13550 m to 11635 m (14% reduction), and the clock Ctotal decrease from 25.8 pf to 21.87 pf (15% reduction). In this thesis, Chapter 1 introduces the background, the applications of panel displays, and literature reviews. The process of a-Si:H TFT, the parameter extractor, and operations of the basic ASG driver circuit are shown in Chapter 2. Chapter 3 illustrates the multi-objective evolutionary algorithm as well as the unified optimization framework and give an example to explain the programs and file formation. In Chapter 4, we use the optimized method based on the MOEA to design a six-stage ASG driver circuit. Each stage of the ASG driver circuit has 17 a-Si:H TFTs and 4 capacitors. After that, we apply a novel multi-level clock driving to the optimized ASG driver circuit and fabricate the sample to be measured. In Chapter 5, we further design a twelve-stage ASG driver circuit by using the optimized method based on the MOEA. Each stage of the ASG driver circuit has 13 a-Si:H TFTs and 2 capacitors, and the sample of this ASG driver circuit is fabricating. Chapter 6 will conclude this study and give the future works. Overall, in this thesis, we have successfully designed a six-stage ASG driver circuit by using optimized method based on the MOEA. To improve the power consumption of panel display and characteristics of the ASG driver circuit, we have proposed the 3-level clock driving method. The fall time has about 50% reduction, and it can increase the contrast ratio of panel displays. Ripple become more smoother, and it can increase the stability of panel displays. The most important is we have fabricated the sample of optimized ASG driver circuit with the display manufacturer in Taiwan and the measured data also has a good agreement and feasibility with our researches. Moreover, we added more objectives, and designed a twelve-stage ASG driver circuit by using optimized method based on the MOEA. We have successfully improved all characteristics of the ASG driver circuit at the same time, such as amplitude of the fall time, the total width of TFTs and the clock Ctotal have over 10% reduction, the ripple has 7% reduction and the rise time also has 9% reduction. This study can apply to medium or large panel products with high performance and competitiveness. With the increasing of specification requirements, ASG driver circuit designs are getting more and more complex. Innovation of the optimized method based on the MOEA in this study can be continuously discussed in the future. The designed of the novel clock drivings is also one of key techniques to improve characteristics of ASG driver circuits.
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