Development of Low Temperature Cu Bonding and Heterogeneous Integration Platform
|關鍵字:||低溫接合;三維積體電路;異質整合;low temperture bonding;three dimensional integrated circuit;heterogeneous integration|
在低溫金屬接合研發中，本研究以暫態液相接合為出發；選用低熔點金屬-銦、錫作為接合材料，接合溫度介於160 °C ~220 °C。並且使用剪力測試，探討熱壓接合參數(溫度、壓力、時間)跟強度之間的關係。在一系列的實驗結果中發現，熱壓接合的情況下接合溫度跟接合時間都不是主要影響強度的因素，推測影響因素為表面金屬氧化層。由於超音波震盪可以去除表面氧化層，因此採用超音波輔助接合測試本實驗架構，最後驗證接合強度的確大幅度提升。
相較於銅柱凸塊暫態液相接合，固相薄膜接合可以有較少的製程步驟並且可以達到更高的密度、更小的間距。本研究中使用表面薄膜鈍化層保護銅防止氧化，以便實行低溫接合。首先在鈍化層的選擇中，考慮自我擴散以及互相擴散所需之能量消耗，探討不同鈍化層跟銅之間的互相擴散行為。其中包含了(1)表面自我擴散 (2)內部體積自我擴散 (3)空缺生成 (4)藉由空隙之互相擴散 (5)藉由空缺所進行之取代型互相擴散。
This dissertation focuses on researches of three-dimensional integrated circuit, including development of key technologies and using technologies for the construction of heterogeneous integration platform. Studies focus on the physical mechanism of bonding technology and its applications, including two parts: (1) ultra-low temperature metal bonding technology, and (2) development of the heterogeneous integration platform through polymer bonding. The newly developed bonding technology can solve several current bottlenecks, such as thermal budget and spacing miniaturization. On the other hand, the proposed heterogeneous integration platform can be applied to various micro-electromechanical systems and different substrates. In low temperature metal bonding, this study used the transient liquid phase connection as the starting material. The metal with low melting point - indium and tin were used as the bonding medium. Bonding temperature was set between 160 °C and 220 ° C. In thermal compression bonding method, the relationship between the bonding parameters (temperature, pressure, and time) and the bonding strength was further discussed through shear tests. After a series of experimental results, in the case of thermal compression bonding, it was found that bonding temperature and bonding time are not the dominant factors. The dominant factor may be the existence of surface oxide layer. Since ultrasonic vibration could remove surface oxide layer, the experimental structure was tested through ultrasonic-assisted bonding. As the results, the bonding strength was improved significantly. Further, in comparison to transient liquid phase, solid-state film bonding can have fewer process steps, higher density, and smaller pitch. In this study, a surface passivation layer was used to protect copper from oxidation. A low temperature bond was achieved because of the passivation layer. At first, in the selection of passivation layer, diffusion behavior between different passivation layers and Cu was investigated by means of energy consumption in both self-diffusion and inter-diffusion: (1) surface self-diffusion, (2) interior bulk self-diffusion, (3) vacancy formation energy, (4) inter-diffusion through interstitial, and (5) inter-diffusion through substitution. Finally, Ti and Pd were used as the passivation layer for following Cu-to-Cu bonding test and electrical analysis. Cu layers with Ti and Pd passivation were successfully bonded at 180 °C and 150 °C, respectively. Kelvin structure was used to carry out electrical measurement and reliability test. Electrical results showed good consistency in the resistance values, which proved that the structure has good endurance against environmental degradation. In the second part of this dissertation “chip-level heterogeneous integration platform”, chip-level post process was demonstrated to achieve heterogeneous integration platform of diced chips. This study proposes a carrier wafer made by dry film lithography, which allows multiple dummy chips to implement lithography, silicon perforation, metal wiring and other wafer-level process validation. Finally, the vertical connection of the heterogeneous integrated chip can be achieved.
|Appears in Collections:||Thesis|