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dc.contributor.author張博珣zh_TW
dc.contributor.author張錫嘉zh_TW
dc.contributor.authorChang, Po-Hsunen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2018-01-24T07:38:36Z-
dc.date.available2018-01-24T07:38:36Z-
dc.date.issued2016en_US
dc.identifier.urihttp://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070350256en_US
dc.identifier.urihttp://hdl.handle.net/11536/139891-
dc.description.abstract近年來,通訊系統中的通道編碼領域研究,特別關注在高吞吐率以及低功率消耗這兩方面,其中,在各種類型的編碼方式中,渦輪編碼器由於其優異的解碼效果而廣受重視。然而,傳統的渦輪編碼器,在高編碼率的情況下,會有解碼速度降低以及複雜度提升的問題。由於碼率為$1/(k+1)$的互反雙重碼對應到的迴旋碼碼率是$k/(k+1)$,在$k$大於1的情況下,使用互反雙重碼可達到簡化硬體複雜度的效果,反之,在碼率低於$1/2$的情況下,使用互反雙重碼的硬體複雜度會比迴旋碼來的高。在本篇論文中,我們提出了使用radix-4傳統柵欄以及互反雙重柵欄的的混合架構來達到高速度以及低複雜度的渦輪碼。此外,為了打破互反雙重柵欄在應用上需要使用週期性打孔的迴旋碼的限制,一種我們稱之為零補丁的方法也會在本論文中提出。 在本論文中提出的解碼器架構適用於LTE-A的標準,包含了其中總共188種的編碼長度,以及從$1/3$ 到 $0.95$的編碼率,此設計都能使用。本設計經由台積電的28nm高效能製程下線,晶片預計會在數個月之後返回。從post-layout的結果來看,我們提出的設計可在263MHz的操作頻率下在執行六次疊代解碼後達到333Mbps的吞吐率,在整體晶片面積 $1.96mm^2$ 中佔了 $1.08mm^2$的大小功率消耗為295.57mW,能源效率為0.148(nJ/bit/iter)。zh_TW
dc.description.abstractIn recent years, the channel coding research in wireless communication targets for the high throughput transmission and low power consumption. Among the various kinds of codes, turbo codes are famous for the capacity-approaching performance. However, the traditional turbo decoder dealing with the high rate code encounters the problem of degradation of decoding speed. Since the reciprocal dual codes with code rate equaling to $1/(k+1)$ correspond to the code rate $k/(k+1)$ convolutional codes, the reciprocal dual codes can simplify the trellis while $k$ is larger than 1. On the other hand, the reciprocal dual codes are more complex when the code rate is less than $1/2$. In this thesis, the architecture of hybrid trellis controller between radix-4 conventional trellis and radix-4 reciprocal dual trellis is proposed for high speed and low complexity turbo codes. Also, to break through the limit of periodical puncture pattern in using reciprocal dual trellis, the zero patch method is proposed. In this thesis, the proposed decoder architecture is applied for LTE-A standard, which allows the 188 kinds of code length and the code rate is ranged from $1/3$ to $0.95$. Moreover, the design is fabricated in TN28HPM process, and the chip will be back in a few month. The post-layout simulations shows the proposed decoder could achieve 333Mbps at 6 iteration under 263MHz operating frequency. The core area is $1.08mm^2$, and draws 295.57mW of power with the energy efficiency of 0.148(nJ/bit/iter).en_US
dc.language.isoen_USen_US
dc.subject渦輪編碼器zh_TW
dc.subject互反雙重柵欄zh_TW
dc.subjectQPP交織器zh_TW
dc.subject高編碼率zh_TW
dc.subjectTurbo decoderen_US
dc.subjectReciprocal dual trellisen_US
dc.subjectquadratic permutation polynomial interleaveren_US
dc.subjectHigh code rateen_US
dc.title使用零補丁技巧之雙重柵欄渦輪解碼器設計zh_TW
dc.titleTurbo Decoder Design using Zero Patching Scheme in Hybrid Trellis Architectureen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis