標題: 有效面積使用之快速鎖定 全數位鎖相迴路
Area-Efficient Fast-Locking All Digital Phase-Locked Loops
作者: 陳柏翰
洪崇智
Chen,Po-Han
Hung,Chung-Chih
電機工程學系
關鍵字: 全數位;鎖相迴路;快速鎖定;面積;數位濾波器;ALL-DIGITAL;PLL;FAST-LOCKING;AREA;DIGITAL PLL
公開日期: 2016
摘要: 鎖相迴路存在於各式各樣電路之中,發展歷史悠久,而現今積體電路大量使用且成熟,鎖相迴路更是攜帶式、通訊用等電子產品中不可或缺的角色,為系統提供穩定持續時脈之核心元件,使電路內各模組得以一致的運作、溝通。隨著先進製程開發,對於傳統類比鎖相迴路來說晶片面積無法顯著縮小、且設計成本相對提高,被動元件面積的消耗成為無法善用先進製程優勢的主因;故近期研究方向為數位式鎖相迴路,利用數位電路改善類比式電路之缺陷,取代被動元件、節省面積,使電路能快速有效的隨製程複製、微縮,亦降低人力設計上的時間成本。然而數位系統複電路雜度高,亦有可能造成更多的功率消耗與面積使用,所以在電路設計的考量中,節能與小面積之特點是不可或缺的。 在本篇論文中,以全客戶式設計完成全數位式鎖相迴路,第一顆晶片設計概念為跳脫傳統類比迴路線性設計的迷思,利用計數器搭配邏輯判斷轉換不同工作階段,達成快速地鎖定;而第二顆晶片以第一顆晶片電路為基礎,採用單調性數位控制單元所構成的環形數位控制振盪器,振盪頻率範圍為540MHz~1250MHz。 兩顆晶片頻率皆鎖定至800MHz;第一顆晶片的量測結果,時脈抖動為24ps的峰對峰值時間抖動(Peak to Peak jitter),功率消耗為13.2mW,核心面積為0.077mm¬2而第二顆晶片的模擬平均峰對峰值時間抖動(Peak to Peak Jitter)為21.6ps,功率消耗為11.2mW,核心面積為0.081mm¬2
Phase-locked loops (PLL) are widely used for many applications, such as system clock recovery and wireless- communication synthesizers. Nowadays, the strong demand of portable devices and consumer electronics make the PLL play an important role in electronic products. Moreover, converting analog circuits to digital systems has become a main development trend. Without analog passive elements, resistors and capacitances, it is much easier for designers to adapt their circuits to suit the scaling process technology. The complexity of logic circuits may cause more energy consumption and materials wasting in the manufacturing process. Therefore, power dissipation and area cost should be main concerns in digital circuit design. In this thesis, we implement the first ADPLL by using full-custom design flow. Utilizing counters as frequency controllers and switching among different working modes can help to achieve fast locking. The design in the second chip is based on the first implementation with addition of fine phase tuning. Both DCOs with ring structures are made of digitally controlled delay elements. They can generate output clocks from 540 MHz to 1.25 GHz. Both chips are designed to lock at 800MHz by 0.18μm CMOS process. With 1.8 V supply voltage, the power dissipation of the first ADPLL is 13.2mW with peak-to-peak jitter of 24ps and core area of 0.077 mm2. For the second chip, the peak-to-peak jitter is 21.6ps and the total power dissipation is 11.2mW in a core area of 0.081 mm2
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070350717
http://hdl.handle.net/11536/139713
Appears in Collections:Thesis