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dc.contributor.author邱奕儒zh_TW
dc.contributor.author張翼zh_TW
dc.contributor.author馬哲申zh_TW
dc.contributor.authorChiu, Yi-Juen_US
dc.contributor.authorChang, Edward-Yien_US
dc.contributor.authorMaa, Jer-Shenen_US
dc.date.accessioned2018-01-24T07:37:33Z-
dc.date.available2018-01-24T07:37:33Z-
dc.date.issued2015en_US
dc.identifier.urihttp://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070258128en_US
dc.identifier.urihttp://hdl.handle.net/11536/139162-
dc.description.abstract作為一個前景看好的半導體材料,近年來氮化鎵在半導體產業 中獲得了越來越多的關注,由於有著較大的能隙寬度、良好的電子 遷移率、快速的飽和電子速度與較高溫的操作容忍度,使得氮化鎵 成為製作高頻功率元件的首選材料。而隨著操作頻率的不斷提高, 電路內的寄生效應對於元件表現的影響也越發顯著,為了維持良好 的元件特性,如何降低電路中的寄生電感就成為了一個相當重要的 課題,而背向通孔接地製程就是其中能降低寄生電感效應的一個好 方法。一般而言, 碳化矽背向通孔的製作方式有雷射剝蝕與乾式蝕 刻兩種,與雷射剝蝕製程相較之下,乾式蝕刻由於需要將晶片磨薄 與製作蝕刻遮罩層而使製程步驟較為複雜,但由於是同時蝕刻所有 的背向導通孔,因此當未來晶片的尺寸越來越大時, 乾式蝕刻的製 程將會更顯效率。故本研究以乾式蝕刻的方式作為製程方法。 本研究探討整個背向通孔製程的各個步驟,由晶片與製程載具 的黏合到通孔蝕刻完成後的背金屬電鍍。此外也探討了在碳化矽背 向通孔中最常見的問題,蝕刻柱狀物的形成與避免。 製程後的直流與高頻量測結果顯示了 在加入了背向通孔製程後 元件的直流特性並無衰減,而由高頻的量測結果則可看出元件的高頻 功率表現有所提升, 輸出功率 (Pout) 由 36dBm(3.3W/mm) 提升至 36.9dBm(4.1W/mm),增益(Gain)由 14.5dB 提升至 17dB,而功率注入效率則由 45%提升至 46%, 證實了背向通孔製程對於高頻功率元件性 能表現的價值。zh_TW
dc.description.abstractAs a promising material, GaN attracts a lot of research attentions in semiconductor industry. Its excellent properties, such as wide bandgap, high electron mobility, high saturation velocity and high maximum operating temperature make it the most attractive material for high frequency and high power devices. Along with increasing operating frequency, the parasitic effect becomes a crucial issue for high-frequency devices. To improve device performance, parasitic inductance must be suppressed. One good method to reduce parasitic inductance is backside via process. There are two methods to fabricate backside via holes in SiC substrate, laser ablation and dry etching. Dry etching process is more complex than laser ablation due to its time-consuming thinning and etching-mask fabrication. However, due to its simultaneous etching of each via holes, dry etching is more compatible with the increasing wafer size. In this study, dry etching process is selected to fabricate the via holes in SiC substrate. This study investigates the whole backside process from wafer mounting to the backside metal plating. Pillar formation issue, one of common problems for backside via dry etching process, is also discussed in this study. The DC and RF property measurements showed that the DC performance does not degrade after backside via process. The RF power performance shows the output power (Pout) increases from 36 dBm(3.3W/mm) to 36.9 dBm(4.1 W/mm), the power gain increases from 14.5 dB to 17 dB, and the power added efficiency (PAE) increases from 45% to 46%. The improvement evidenced the feasibility of backside via process to RF power devices.en_US
dc.language.isoen_USen_US
dc.subject氮化鎵zh_TW
dc.subject碳化矽zh_TW
dc.subject背向通孔製程zh_TW
dc.subjectGaNen_US
dc.subjectSiCen_US
dc.subjectBackside Viaen_US
dc.title應用於氮化鎵高頻功率元件之碳化矽基板背向通孔製程zh_TW
dc.titleSiC Backside Via Process for GaN RF Power Device Applicationen_US
dc.typeThesisen_US
dc.contributor.department照明與能源光電研究所zh_TW
Appears in Collections:Thesis