Title: Simultaneous power supply planning and noise avoidance in floorplan design
Authors: Chen, HM
Huang, LD
Liu, IM
Wong, MDF
Department of Electronics Engineering and Institute of Electronics
Keywords: floorplanning;physical design;power supply planning;signal integrity
Issue Date: 1-Apr-2005
Abstract: With today's advanced integrated circuit manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single system on a chip. However, without careful power supply planning in layout, the design of chips will suffer from local hot spots, insufficient power supply, and signal integrity problems. Postfloorplanning or postroute methodologies in solving power delivery and signal integrity problems have been applied but they will cause a long turnaround time, which adds costly delays to time-to-market. In this paper, we study the problem of simultaneous power supply planning and noise avoidance as early as in the floorplanning stage. We show that the problem of simultaneous power supply planning and noise avoidance can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With a slight increase of total wirelength, we achieve almost no static IR (voltage)-drop requirement violation in meeting the current and power demand requirement imposed by the circuit blocks compared with a traditional floorplanner and 45.7% of improvement on a Delta I noise constraint violation compared wit the approach that only considers power supply planning.
URI: http://dx.doi.org/10.1109/TCAD.2005.844088
ISSN: 0278-0070
DOI: 10.1109/TCAD.2005.844088
Volume: 24
Issue: 4
Begin Page: 578
End Page: 587
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