標題: Modeling geometry-dependent floating-body effect using body-source built-in potential lowering for SOI circuit simulation
作者: Su, P
Lee, W
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: floating-body effect;body-source built-in potential lowering;SOICMOS;circuit simulation
公開日期: 1-四月-2005
摘要: This paper presents a compact silicon-on-insulator (SOI) model to capture the geometry-dependent floating-body effect using the body-source built-in potential lowering approach. This physically accurate model circumvents the modeling challenge imposed by the trend of the coexistence of partial-depletion (PD) and full-depletion (FD) devices in a single SOI chip by considering short-channel, reverse short-channel and reverse narrow-width floating-body effects. The implication on circuit simulation, under the unified Berkeley short-channel IGFET model-silicon-on-insulator (BSIMSOI) framework, has also been addressed. This geometry-dependent body-source built-in potential lowering model will further enhance the device design of scaled SOI complementary metal-oxide-semiconductor (CMOS) below 100 nm.
URI: http://dx.doi.org/10.1143/JJAP.44.2366
http://hdl.handle.net/11536/13842
ISSN: 0021-4922
DOI: 10.1143/JJAP.44.2366
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS
Volume: 44
Issue: 4B
起始頁: 2366
結束頁: 2370
顯示於類別:期刊論文


文件中的檔案:

  1. 000229095700057.pdf