Title: ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology
Authors: Ker, MD
Chuang, CH
Lo, WY
電機學院
College of Electrical and Computer Engineering
Keywords: CMOS;diode;electrostatic discharge (ESD) implantation;ESD protection;snapback breakdown
Issue Date: 1-May-2005
Abstract: One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18 mu m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I-t2) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.
URI: http://dx.doi.org/10.1109/TSM.2005.845100
http://hdl.handle.net/11536/13770
ISSN: 0894-6507
DOI: 10.1109/TSM.2005.845100
Journal: IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
Volume: 18
Issue: 2
Begin Page: 328
End Page: 337
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