標題: A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration
作者: Liu, HC
Lee, ZM
Wu, JT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: analog-digital conversion;calibration;mixed analog-digital integrated circuits
公開日期: 1-五月-2005
摘要: This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-mu m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8 x 3.6 mm(2), and the power consumption is 370 mW with a single 2.5-V supply.
URI: http://dx.doi.org/10.1109/JSSC.2005.845986
http://hdl.handle.net/11536/13754
ISSN: 0018-9200
DOI: 10.1109/JSSC.2005.845986
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 40
Issue: 5
起始頁: 1047
結束頁: 1056
顯示於類別:期刊論文


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  1. 000228773600002.pdf