|標題:||A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology|
|作者:||Hsieh, E. R.|
Hung, C. M.
Wang, T. Y.
Chung, Steve S.
Huang, R. M.
Tsai, C. T.
Yew, T. R.
Department of Electronics Engineering and Institute of Electronics
|摘要:||Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, A(vt), A(gm), in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.|
|期刊:||2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)|
|Appears in Collections:||Conferences Paper|