|標題:||Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power Applications|
|作者:||Hsieh, E. R.|
Lin, Y. S.
Zhao, Y. B.
Liu, C. H.
Chien, C. H.
Chung, Steve S.
Department of Electronics Engineering and Institute of Electronics
|摘要:||A new concept of the structure design with an alignment between the maximum band-to-band tunneling rate and electric field has been proposed to enhance the performance of TFETs. It was found that the specific gate of TFET to form an obtuse shape can dramatically improve the on-current of TFET, with over 4 order improvement in comparison to planar ones. This complementary TFET (CTFET) was also demonstrated by SRAM as a benchmark, with SiGe/Si integrated with III-V on Si substrate. In order to increase WNM and RSNM of CTFET SRAM, a new scheme has been adopted, in which SRAM has been successfully demonstrated with operating bias down to 0.3V.|
|期刊:||2015 SILICON NANOELECTRONICS WORKSHOP (SNW)|
|Appears in Collections:||Conferences Paper|