標題: Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
作者: Ker, MD
Wu, CY
Chang, HH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-四月-1996
摘要: There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines, The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid the unexpected ESD damages on internal circuits, Experimental results show that it can perform excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit, The device characteristics under high-temperature environment of up to 150 degrees C is also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.
URI: http://hdl.handle.net/11536/1358
ISSN: 0018-9383
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 43
Issue: 4
起始頁: 588
結束頁: 598
顯示於類別:期刊論文


文件中的檔案:

  1. A1996UC51100012.pdf