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dc.contributor.authorYang, Yu-Mingen_US
dc.contributor.authorTam, King Hoen_US
dc.contributor.authorJiang, Iris Hui-Ruen_US
dc.date.accessioned2017-04-21T06:49:13Z-
dc.date.available2017-04-21T06:49:13Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4503-3520-1en_US
dc.identifier.issn0738-100Xen_US
dc.identifier.urihttp://dx.doi.org/10.1145/2744769.2744812en_US
dc.identifier.urihttp://hdl.handle.net/11536/135740-
dc.description.abstractFor nanometer design, conventional timing analysis may generate over-optimistic results on criticality-dependent paths. A late arrival time at the data input of a flip-flop lengthens the propagation delay from the clock pin to the data output of this flip-flop, thus degrading the timing margins of paths launching from this flip-flop. To remove the optimism, in this paper, we first propose a simple yet effective triangle model to characterize the criticality-dependency effect. Then, we devise a novel criticality-dependency-aware timing analysis flow, which is seamlessly integrated with the common static timing analysis flow. Experimental results show that our approach can effectively analyze the criticality-dependency effect: Based on the proposed triangle model, we can accurately identify all timing-risky Hip Hops and capture the induced timing margin degradation.en_US
dc.language.isoen_USen_US
dc.subjectCriticality-dependency effecten_US
dc.subjectTiming analysisen_US
dc.titleCriticality-Dependency-Aware Timing Characterization and Analysisen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1145/2744769.2744812en_US
dc.identifier.journal2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000370268400169en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper