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dc.contributor.authorLin, Chia-Yien_US
dc.contributor.authorChen, Hung-Mingen_US
dc.date.accessioned2017-04-21T06:48:38Z-
dc.date.available2017-04-21T06:48:38Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-6455-5en_US
dc.identifier.issn1948-3287en_US
dc.identifier.urihttp://hdl.handle.net/11536/135594-
dc.description.abstractThis paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many long scan chain switching activities. Based on two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. The proposed scheme skips many unnecessary don\'t care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed scheme illustrate the significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC\'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead and very few extra pins, and the power reduction is over 97%.en_US
dc.language.isoen_USen_US
dc.subjectScan chainen_US
dc.subjectTest-costen_US
dc.subjectlow poweren_US
dc.titleA Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reductionen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010)en_US
dc.citation.spage237en_US
dc.citation.epage243en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000393299700037en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper