標題: A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI
作者: Zimmer, Brian
Lee, Yunsup
Puggelli, Alberto
Kwak, Jaehwa
Jevtic, Ruzica
Keller, Ben
Bailey, Steven
Blagojevic, Milovan
Chiu, Pi-Feng
Hanh-Phuc Le
Chen, Po-Hung
Sutardja, Nicholas
Avizienis, Rimas
Waterman, Andrew
Richards, Brian
Flatresse, Philippe
Alon, Elad
Asanovic, Krste
Nikolic, Borivoje
交大名義發表
National Chiao Tung University
關鍵字: Adaptive clock;DC-DC conversion;dynamic voltage and frequency scaling (DVFS);fully integrated converter;integrated voltage regulator;noninterleaved;RISC-V;simultaneous-switching;switched-capacitor
公開日期: Apr-2016
摘要: This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.
URI: http://dx.doi.org/10.1109/JSSC.2016.2519386
http://hdl.handle.net/11536/135112
ISSN: 0018-9200
DOI: 10.1109/JSSC.2016.2519386
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 51
Issue: 4
起始頁: 930
結束頁: 942
Appears in Collections:Conferences Paper