Title: A Layout-Aware Test Methodology for Silicon Interposer in 3D System-in-a-Package
Authors: Gu, Ruei-Ting
Ho, Cheng-You
Li, Katherine Shu-Min
Ho, Yingchieh
Chen, Liang-Bi
Hsieh, Kai-Yang
Huang, Jiun-Jie
Cheng, Bo-Chuan
Wang, Sying-Jyan
Gao, Zih-Huan
Department of Electronics Engineering and Institute of Electronics
Issue Date: 2013
Abstract: In this paper, we propose an efficient silicon interposer pre-test methodology, which is based on the layout-aware ripple baseline algorithm for System-in-a-Package (SiP). The proposed methodology uses FPGA as our test vehicle that can test all interconnects at once without any test probes. The test interposer is synthesized according to the given layout of the target interposers, which provide microbumps and solder balls with pitches, and the test interposers are connected to the upper test side of the target interposers. Thus the test loops, which cover all interconnections of the target interposers, are built by connecting the test interposers and the target interposers. The bottom side of the target interposer is connected to an FPGA as the tester that provides test patterns to the target interposer and compares the result to identify the faulty interconnections of the target interposer. Experimental results show our method is both effective and efficient with achieving 100% fault coverage for all interposers. With scaling to more than hundreds of hundreds interposers, our method is still effective within two to three hours.
URI: http://hdl.handle.net/11536/134736
ISBN: 978-1-4673-3037-4
ISSN: 2378-8593
Appears in Collections:Conferences Paper