Title: A 16kB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS
Authors: Kuo, Ming-Zhang
Hsieh, Henry
Dhong, Sang
Yang, Ping-Lin
Lin, Cheng-Chung
Tseng, Ryan
Huang, Kevin
Wang, Min-Jer
Hwang, Wei
Department of Electronics Engineering and Institute of Electronics
Keywords: Cross-coupled PMOS-pair;DVFS;independently controlled precharge-and-write driver (ICPW);SRAM
Issue Date: 2014
Abstract: This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um(2) high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltage-Temperature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.
URI: http://hdl.handle.net/11536/134704
ISBN: 978-1-4799-3286-3
Appears in Collections:Conferences Paper