標題: Power and substrate noise tolerance of configurable embedded memories in SoC
作者: Chang, MF
Wen, KA
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: ROM;SRAM;substrate noise;supply noise
公開日期: 1-八月-2005
摘要: When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 mu m CMOS process are studied.
URI: http://dx.doi.org/10.1007/s11265-005-6252-4
http://hdl.handle.net/11536/13463
ISSN: 0922-5773
DOI: 10.1007/s11265-005-6252-4
期刊: JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Volume: 41
Issue: 1
起始頁: 81
結束頁: 91
顯示於類別:期刊論文


文件中的檔案:

  1. 000229936200007.pdf