標題: A software-hardware co-implementation of MPEG-4 Advanced Video Coding (AVC) decoder with block level pipelining
作者: Wang, SH
Peng, WH
He, YW
Lin, GY
Lin, CY
Chang, SC
Wang, CN
Chiang, T
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: MPEG-4;advanced video coding (AVC);H.264;joint video team (JVT);software-hardware co-implementation;task partition;MB level pipelining
公開日期: 1-八月-2005
摘要: We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.
URI: http://dx.doi.org/10.1007/s11265-005-6253-3
http://hdl.handle.net/11536/13431
ISSN: 0922-5773
DOI: 10.1007/s11265-005-6253-3
期刊: JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Volume: 41
Issue: 1
起始頁: 93
結束頁: 110
顯示於類別:期刊論文


文件中的檔案:

  1. 000229936200008.pdf