Title: 3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications
Authors: Wang, I-Ting
Chang, Chih-Cheng
Chiu, Li-Wen
Chou, Teyuh
Hou, Tuo-Hung
Department of Electronics Engineering and Institute of Electronics
Keywords: hardware neural network;electronic synapse;three dimensional;RRAM
Issue Date: 9-Sep-2016
Abstract: The implementation of highly anticipated hardware neural networks (HNNs) hinges largely on the successful development of a low-power, high-density, and reliable analog electronic synaptic array. In this study, we demonstrate a two-layer Ta/TaOx/TiO2/Ti cross-point synaptic array that emulates the high-density three-dimensional network architecture of human brains. Excellent uniformity and reproducibility among intralayer and interlayer cells were realized. Moreover, at least 50 analog synaptic weight states could be precisely controlled with minimal drifting during a cycling endurance test of 5000 training pulses at an operating voltage of 3 V. We also propose a new state-independent bipolar-pulse-training scheme to improve the linearity of weight updates. The improved linearity considerably enhances the fault tolerance of HNNs, thus improving the training accuracy.
URI: http://dx.doi.org/10.1088/0957-4484/27/36/365204
ISSN: 0957-4484
DOI: 10.1088/0957-4484/27/36/365204
Volume: 27
Issue: 36
Appears in Collections:Articles