標題: Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test
作者: Ker, MD
Hsu, SF
電機學院
College of Electrical and Computer Engineering
關鍵字: holding voltage;latchup;silicon controlled rectifier (SCR);system-level electrostatic discharge (ESD) test;transient-induced latchup (TLU)
公開日期: 1-八月-2005
摘要: The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-mu m CMOS technology.
URI: http://dx.doi.org/10.1109/TED.2005.852728
http://hdl.handle.net/11536/13419
ISSN: 0018-9383
DOI: 10.1109/TED.2005.852728
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 52
Issue: 8
起始頁: 1821
結束頁: 1831
顯示於類別:期刊論文


文件中的檔案:

  1. 000230802200021.pdf