標題: ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS
作者: Ker, MD
Chang, WJ
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: electrostatic discharge (ESD);human body mode (HBM);low-voltage-triggered p-n-p (LVTp-n-p);optical-beam-induced resistance change (OBIRCH);photon emission microscope (EMMI)
公開日期: 1-九月-2005
摘要: Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces with the low-voltage-triggered p-n-p (LVTp-n-p) device in CMOS technology is proposed. The LVTp-n-p, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the p-n-p device, is designed to protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The LVTp-n-p devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-mu m CMOS process have proven that the ESD level of the proposed LVTp-n-p is higher than that of the traditional p-n-p device. Furthermore, layout on LVTp-n-p device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35- and 0.25-mu m CMOS processes have proven that the ESD levels of the LVTp-n-p drawn in the multifinger layout style are higher than that drawn in the single-finger layout style. Moreover, one of the LVTp-n-p devices drawn with the multifinger layout style has been used to successfully protect the input stage of an asymmetric digital subscriber line (ADSL) IC in a 0.25-mu m salicided CMOS process.
URI: http://dx.doi.org/10.1109/TDMR.2005.856500
http://hdl.handle.net/11536/13375
ISSN: 1530-4388
DOI: 10.1109/TDMR.2005.856500
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 5
Issue: 3
起始頁: 602
結束頁: 612
顯示於類別:期刊論文


文件中的檔案:

  1. 000235070500035.pdf