Title: Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors
Authors: Wang, Po-Hao
Tsai, Shang-Jen
Tanjung, Rizal
Lin, Tay-Jyi
Wang, Jinn-Shyan
Chen, Tien-Fu
Department of Computer Science
Keywords: Cache memory;Low voltage;Timing discrepancy;Timing-failure tolerance
Issue Date: Jun-2016
Abstract: Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration. (C) 2016 Elsevier B.V. All rights reserved.
URI: http://dx.doi.org/10.1016/j.vlsi.2016.01.001
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2016.01.001
Volume: 54
Begin Page: 24
End Page: 36
Appears in Collections:Articles