標題: Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
作者: Yu, Kuan-Chin
Fan, Ming-Long
Su, Pin
Chuang, Ching-Te
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: InGaAs/Ge;monolithic 3-D;logic circuits;SRAM;interlayer coupling
公開日期: 1-Mar-2016
摘要: This paper evaluates monolithic 3-D logic circuits and 6T SRAMs composed of InGaAs-n/Ge-p ultra-thin-body MOSFETs while considering interlayer coupling through TCAD mixed-mode model. This paper indicates that monolithic 3-D InGaAs/Ge logic circuits provide equal leakage and better delay performance compared with planar 2-D structure through optimized 3-D layout. The monolithic 3-D InGaAs/Ge 6T SRAMs can simultaneously improve the cell stability and performance through optimized 3-D layout. We suggest two 3-D SRAM layout designs for high performance and low power applications, respectively. Moreover, with optimized 3-D layout designs, InGaAs/Ge logic circuits exhibit larger delay improvement, and the 6T SRAMs exhibit larger read access time and time-to-write improvement compared with Si counterparts.
URI: http://dx.doi.org/10.1109/JEDS.2016.2524567
http://hdl.handle.net/11536/133497
ISSN: 2168-6734
DOI: 10.1109/JEDS.2016.2524567
期刊: IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
Volume: 4
Issue: 2
起始頁: 76
結束頁: 82
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