標題: Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
作者: Liu, Tung-Yu
Pan, Fu-Ming
Sheu, Jeng-Tzong
材料科學與工程學系
分子醫學與生物工程研究所
Department of Materials Science and Engineering
Institute of Molecular Medicine and Bioengineering
關鍵字: Gate-all-around (GAA);poly-Si;junctionless (JL);nanowire (NW);sidewall spacer;transistor
公開日期: 九月-2015
摘要: A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high I-on/I-off current ratio of 7 x 10(8) (V-G = 4 V and V-D = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.
URI: http://dx.doi.org/10.1109/JEDS.2015.2441736
http://hdl.handle.net/11536/133385
ISSN: 2168-6734
DOI: 10.1109/JEDS.2015.2441736
期刊: IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
Volume: 3
Issue: 5
起始頁: 405
結束頁: 409
顯示於類別:期刊論文