標題: Efficient Designs of Multiported Memory on FPGA
作者: Lai, Bo-Cheng Charles
Lin, Jiun-Liang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Block RAM (BRAM);field-programmable gate array (FPGA);multiported memory;performance
公開日期: Jan-2017
摘要: The utilization of block RAMs (BRAMs) is a critical performance factor for multiported memory designs on field-programmable gate arrays (FPGAs). Not only does the excessive demand on BRAMs block the usage of BRAMs from other parts of a design, but the complex routing between BRAMs and logic also limits the operating frequency. This paper first introduces a brand new perspective and a more efficient way of using a conventional two reads one write (2R1W) memory as a 2R1W/4R memory. By exploiting the 2R1W/4R as the building block, this paper introduces a hierarchical design of 4R1W memory that requires 25% fewer BRAMs than the previous approach of duplicating the 2R1W module. Memories with more read/write ports can be extended from the proposed 2R1W/4R memory and the hierarchical 4R1W memory. Compared with previous xor-based and live value table-based approaches, the proposed designs can, respectively, reduce up to 53% and 69% of BRAM usage for 4R2W memory designs with 8K-depth. For complex multiported designs, the proposed BRAM-efficient approaches can achieve higher clock frequencies by alleviating the complex routing in an FPGA. For 4R3W memory with 8K-depth, the proposed design can save 53% of BRAMs and enhance the operating frequency by 20%.
URI: http://dx.doi.org/10.1109/TVLSI.2016.2568579
http://hdl.handle.net/11536/133220
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2016.2568579
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 25
Issue: 1
起始頁: 139
結束頁: 150
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