標題: Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs
作者: Li, YM
Chou, HM
Lee, JW
電信工程研究所
友訊交大聯合研發中心
Institute of Communications Engineering
D Link NCTU Joint Res Ctr
關鍵字: coverage ratio;device structure;fabrication;fin field-effect transistor (FinFET);gate capacitance;nanodevice;nanowire;omega-shaped-gate;on/off ratio;process technique;quantum correction model;semiconductor devices;subthreshold swing (SS);surrounding gate;three-dimensional (3-D) simulation;turn-on resistance
公開日期: 1-九月-2005
摘要: In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowing, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire Fin FETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.
URI: http://dx.doi.org/10.1109/TNANO.2005.851410
http://hdl.handle.net/11536/13314
ISSN: 1536-125X
DOI: 10.1109/TNANO.2005.851410
期刊: IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume: 4
Issue: 5
起始頁: 510
結束頁: 516
顯示於類別:會議論文


文件中的檔案:

  1. 000231809500005.pdf