標題: Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process
作者: Ker, MD
Hsu, KC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: charged device model (CDM);electrostatic discharge (ESD);native NMOS;silicon-controlled rectifier (SCR)
公開日期: 1-九月-2005
摘要: In order to quickly discharge the electrostatic discharge (ESD) energy and to efficiently protect the ultrathin gate oxide, a novel native-negative-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled rectifier (NANSCR) is proposed for on-chip ESD protection in a 0.13-mu m complementary metal oxide semiconductor (CMOS) process with a voltage supply of 1.2 V. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger. A new whole-chip ESD protection scheme realized with the proposed NANSCR devices is also demonstrated with the consideration of pin-to-pin ESD stress. From the experimental results, the trigger voltage, holding voltage, turn-on resistance, turn-on speed, and charged-device-model (CDM) ESD level of NANSCR can be greatly improved, as compared with the traditional low-voltage-triggering SCR (LVTSCR). Under transmission line pulsing (TLP) stress, the gate leakage current of the gate monitor device protected by the proposed NANSCR is monitored after each TLP pulse, whereas the gate leakage current is not obviously increased. Therefore, the ultrathin gate oxide of the input stage can be safely protected by the new proposed NANSCR against ESD stress in the nanoscale CMOS technology.
URI: http://dx.doi.org/10.1109/TDMR.2005.853514
http://hdl.handle.net/11536/13304
ISSN: 1530-4388
DOI: 10.1109/TDMR.2005.853514
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 5
Issue: 3
起始頁: 543
結束頁: 554
顯示於類別:會議論文


文件中的檔案:

  1. 000235070500029.pdf