Title: A background comparator calibration technique for flash analog-to-digital converters
Authors: Huang, CC
Wu, JT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: comparator;flash analog-to-digital converter (ADC);offset calibration
Issue Date: 1-Sep-2005
Abstract: This paper presents a background calibration technique for trimming the input-referred offsets of the comparators in a flash analog-to-digital converter (ADC) without interrupting the ADC's normal operation. For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. Binary feedback is then used to digitally adjust the comparator's offset so that the offset is minimized. All calibration procedures are performed in the digital domain. The calibration performance is characterized by the converging speed of the feedback loop and the offset fluctuation due to the disturbance of the ADC's input. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of the ADC's input, the BCC's offset quantized step size, and the threshold of an internal bilateral peak detector. The offset fluctuation of a BCC can be drastically reduced by employing a windowing mechanism. The use of windowed BCCs in a flash ADC can introduce nonmonotonic-threshold (NMT) effects which include an increase in calibration settling time and an increase in sigma(V-OS). The use of uncorrelated random chopping for neighboring BCCs can ensure the validity of offset detection and mitigate the NMT effects.
URI: http://dx.doi.org/10.1109/TCSI.2005.852198
http://hdl.handle.net/11536/13299
ISSN: 1057-7122
DOI: 10.1109/TCSI.2005.852198
Journal: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 52
Issue: 9
Begin Page: 1732
End Page: 1740
Appears in Collections:Articles


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