標題: ESD protection design for 1-to 10-GHz distributed amplifier in CMOS technology
作者: Ker, MD
Hsiao, YW
Kuo, BJ
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: decreasing-sized distributed ESD (DS-DESD);distributed amplifier (DA);electrostatic discharge (ESD);equal-sized distributed ESD (ES-DESD);resistive ladder
公開日期: 1-Sep-2005
摘要: Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-mu m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 +/- l dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 +/- 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and. high ESD robustness of the DA can be successfully codesigned to meet the application specifications.
URI: http://dx.doi.org/10.1109/TMTT.2005.854208
http://hdl.handle.net/11536/13297
ISSN: 0018-9480
DOI: 10.1109/TMTT.2005.854208
期刊: IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Volume: 53
Issue: 9
起始頁: 2672
結束頁: 2681
Appears in Collections:Conferences Paper


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