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dc.contributor.authorLai, CSen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorLei, TFen_US
dc.contributor.authorChern, HNen_US
dc.date.accessioned2014-12-08T15:02:40Z-
dc.date.available2014-12-08T15:02:40Z-
dc.date.issued1996-05-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/55.491828en_US
dc.identifier.urihttp://hdl.handle.net/11536/1316-
dc.description.abstractA novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated, The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution, The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.en_US
dc.language.isoen_USen_US
dc.titleA novel vertical bottom-gate polysilicon thin film transistor with self-aligned offseten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/55.491828en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume17en_US
dc.citation.issue5en_US
dc.citation.spage199en_US
dc.citation.epage201en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:A1996UH51200003-
dc.citation.woscount9-
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