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dc.contributor.authorYou, KFen_US
dc.contributor.authorWu, CYen_US
dc.date.accessioned2014-12-08T15:02:40Z-
dc.date.available2014-12-08T15:02:40Z-
dc.date.issued1996-05-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://dx.doi.org/10.1016/0038-1101(95)00155-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/1311-
dc.description.abstractDuring plasma etching, a large amount of charging current due to plasma can flow through the gate oxide near the endpoint, resulting in the degradation of thin gate oxide. In this paper, a two-step etching process using reactive ion etching (RIE) following wet etching is proposed to reduce the gate oxide charging current. The characteristics of the proposed process for gate oxide protection are characterized by time-dependent dielectric breakdown (TDDB), high-frequency capacitance-voltage (HFCV), and quasistatic capacitance-voltage (QSCV) measurements. From measurement results, it is shown that degradation of the gate oxide is dramatically eliminated by the proposed two-step etching method as compared with that using pure RIE. Therefore, the proposed two-step etching process can replace the pure dry etching process to reduce the plasma-induced gate oxide damage.en_US
dc.language.isoen_USen_US
dc.titleA novel two-step etching process for reducing plasma-induced oxide damageen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/0038-1101(95)00155-7en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume39en_US
dc.citation.issue5en_US
dc.citation.spage689en_US
dc.citation.epage693en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1996UE25100011-
dc.citation.woscount2-
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