Device Technology and Characterization of Poly-Si Non-Volatile Memory for 3D Stack
|關鍵字:||非揮發性記憶體;三維積體電路;垂直閘極;晶粒邊界;隨機電報雜訊;Non-volatile memory;3D IC;vertical gate;grain boundary;random telegraph_x000d_ noise|
Flash memory is one of the most important elements of electronic products. In order to increase the memory density, memory cell scales down aggressively. At the same time, the technology of using charge trapping layer to replace the floating gate has been developed extensively. There exists limitation on the shrinkage of the charge-trapping memory cell, thus lots of non-charge-trapping memory cells have been proposed, such as MRAM, FeRAM, PCRAM, and RRAM. Among them, RRAM is the most promising candidate. However, the mass production of RRAM is projected in 2020. How to bridge the gap between RRAM and the current flash memory is a good question. Recently, several 3D NAND flash strategies have been proposed by the major players. 3D NAND flash allows more relaxed design rule to store more electrons and reduce disturbance. However, the channel of the 3D NAND flash becomes poly-Si. Therefore, the impact of traps, potential barrier, carrier scattering due to grain boundary on memory cell becomes urgent. This 3-year project concentrates on the vertical-gate poly-Si 3D NAND flash device. The topics include the effect of grain boundary on device variation, process and characterization of 3D NAND flash devices with various poly-Si grain structure and charge trapping layers, the effect of random-telegraph-noise (RTN) due to grain boundaries on memory states, and the characteristics of charge retention and disturbance of the 3D NAND flash device. In the first year of the project, we will focus on 3D simulation of grain boundary effect and process development. In the second year, devices with various grain structures will be characterized and the RTN will be analyzed. In the third year, we will focus on the charge retention, disturbance, and the improvement of memory performance by the charge-trapping-layer engineering. It is predicted that the 3D NAND flash would be mass-produced in 2016. This project provides deep understand of the fundamentals of the nano-scale poly-Si memory cell and the design, process, and characterization of the 3D NAND flash devices. All of them bring benefit to academic research and industry applications.
|Appears in Collections:||Research Plans|