|標題:||鰭狀場效電晶體 (FinFET) 電路之錯誤模型與測試方法|
Fault Modeling and Test Methods for FinFET Ciricuits
Chao Mango Chia-Tso
|關鍵字:||鰭狀場效電晶體;積體電路測試;錯誤模型;FinFET;VLSI testing;fault modeling|
|摘要:||當CMOS技術不斷縮小電晶體元件尺寸，特別是進到22nm以下的技術時，許多重要的晶片製造商如Intel、IBM、及TSMC等皆陸續發表他們在FinFET元件製程的技術。FinFET元件具有許多優異的電性特性。相對傳統的Bulk CMOS而言，它有較低的漏電流、較大的元件開關電流比、高電子移動率、低雜質參雜濃度差異與更小的元件縮小參數。此外，在元件的實現部分，最基本就有兩種元件結構已經被廣泛採用，即栓鎖閘極結構與獨立閘極結構。因著FinFET結構之不同，相對應的FinFET電路設計亦可以多元的設計。許多的設計目標都依序被改善與增進，例如低功耗、高運算速度、多模式工作等等。以學術研究的領域來看，已過的題目大多專注於FinFET元件的設計與相關電路的提出，對於相關量產上所需要的測試方法與流程，該進展仍相當有限，特別是對於已經被發現的專有製程缺陷Gate-LER and Fin-LER等等。
FinFET devices have the advantages of smaller gate leakage, better sub-threshold slope, less random dopant fluctuation, higher mobility and better geometric scalability compared to the conventional bulk devices. The current IC industry has generally considered the FinFET devices as the best candidate of process technologies when going into 22nm node or below, and several major manufacturers, such as Intel, IBM, and TSMC, have kept on announcing their advance in FinFET technologies to gain their leading position in the never-ended device scaling competition. Due to various device implementations of FinFET, such as tied-gate, independent gate and different surface orientations, several new FinFET circuit designs have been proposed for both logic cells and SRAMs to improve its performance, power, area or variability. Even though tremendous research efforts have been put into the FinFET circuit designs during the past few years, seldom research works have discussed the testing-related issues for the corresponding FinFET circuits and FinFET induced defects, such as Gate-LER and Fin-LER. In this project, our objective is to discover the fault models for FinFET logic cells or SRAMs, especially those that cannot be detected by the conventional test methods built for bulk devices, and then develop the corresponding new test methods dedicated for FinFET circuits. In order to achieve this goal, we first need to build a technology-CAD environment to simulate the 3D FinFET devices with tied-gate, independent-gate or different surface orientations. Second, we need to extract the faulty behavior of FinFET devices by injecting corresponding defects in the TCAD simulation and further develop a SPICE model to represent the defective devices, so that its faulty behavior can be successfully simulated at a circuit-level design. Next, based on this SPICE model of defective FinFET devices, we can identify their faulty impact on various types of logic cells designs or SRAM designs, and further evaluate the effectiveness of the conventional and new proposed test methods. Necessary DfT techniques, ATPG techniques, or March algorithms for detecting the defective FinFET devices will also be discussed.
|Appears in Collections:||Research Plans|