標題: The CMP process and cleaning solution for planarization of strain-relaxed SiGe virtual substrates in MOSFET applications
作者: Shieh, MS
Chen, PS
Tsai, MJ
Lei, TF
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2006
摘要: The effects of different polishing pads and slurry solid contents on the SiGe chemical mechanical polish (CMP) process were investigated. By optimizing the polishing conditions, a smooth strained-Si surface on a flattened Si0.8Ge0.2 buffer layer of 0.6 nm can be achieved. The novel cleaning solutions with various surfactants and chelating agents for post-CMP SiGe were studied. There was about 10% current enhancement of the optimal cleaning conditions, showing high performance in particle removal, metallic cleaning, and electrical characteristics. (c) 2005 The Electrochemical Society.
URI: http://hdl.handle.net/11536/12859
http://dx.doi.org/10.1149/1.2149291
ISSN: 0013-4651
DOI: 10.1149/1.2149291
期刊: JOURNAL OF THE ELECTROCHEMICAL SOCIETY
Volume: 153
Issue: 2
起始頁: G144
結束頁: G148
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