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dc.contributor.author黃義傑en_US
dc.contributor.authorHuang, Yi-Jieen_US
dc.contributor.author柯明道en_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2015-11-26T01:02:22Z-
dc.date.available2015-11-26T01:02:22Z-
dc.date.issued2015en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT070250155en_US
dc.identifier.urihttp://hdl.handle.net/11536/127359-
dc.description.abstract現今智能電源技術已經發展並且電子產品中很多積體電路是在高壓(HV)製程中被製造。例如車用IC等,通常使用高壓製程,與低壓(LV)元件相比,高壓電晶體結構較為複雜,這是為了放大操作範圍和崩潰電壓,如此一來使得靜電放電(ESD)防護的設計更加困難和具有挑戰性。 在高壓的靜電放電防護設計中,常會使用橫向擴散電晶體 (lateral diffused MOS, LDMOS),這是常見的高壓電晶體,且與低壓電晶體相比,在同樣的布局大小下,通常高壓靜電防護元件的靜電耐受度表現較差,所以使用高壓防護元件,通常都會放大元件大小以達到要求的靜電耐受度,並且要特別注意均勻導通性。 高壓應用之靜電防護元件提出利用低壓P型場氧化層元件 (LVPFOD) 堆疊的構造在0.5微米高壓絕緣層覆矽 (silicon on insulator, SOI) 製程實現。在面積與靜電防護耐受度的考量下,低壓的靜電防護元件,在單位面積下,有比較好的靜電防護耐受度,使用堆疊方法使整體的導通電壓 (trigger voltage) 與持有電壓 (holding voltage) 往上疊加,使它滿足高壓積體電路的需求,所以堆疊可以是最佳的方法之一。在高壓靜電放電防護設計中,持有電壓是一個重要的考量,當在靜電防護元件的持有電壓低於供給的電壓時,在應用上有可能會發生閂鎖效應 (latchup)。實驗並驗證不同堆疊個數的低壓P型場氧化層元件在高壓應用下可以達到較高的靜電防護耐受度,並且達到閂鎖效應免疫。 在此篇論文中,探討了堆疊的靜電防護元件電阻值大小對人體模型和機器模型電流波形的影響效應,這解釋了堆疊的靜電防護元件電阻對峰值電流和波形震盪的影響非常明顯,特別是在機器模型的測試中。因為機器模型中的負載電阻主要受到堆疊的元件影響,但是人體模型則是受到1.5千歐姆的負載電阻影響,所以機器模型量測到的靜電防護耐受度隨著堆疊的低壓P型場氧化層元件個數增加而增加,而人體模型的靜電防護耐受度則不會隨著堆疊個數而改變,量測到相同的靜電防護耐受度。zh_TW
dc.description.abstractNowadays, the smart power technology has been developed and many integrated circuits (ICs) of electrical products fabricated in a high-voltage (HV) process. Automotive ICs, power management ICs, and driver ICs for various display panels are commonly fabricated in a HV process. HV transistors are fabricated with complicated structure for enlarging the operating range and breakdown voltage, and that makes electrostatic discharge (ESD) protection design more difficult and challenging compared with the low-voltage (LV) devices. In ESD protection design for HV applications, it is common to use lateral diffused MOS (LDMOS) as an ESD protection device. LDMOS is a general HV transistor in a HV process, and its ESD robustness is worse than a LV device’s. Enlarging LDMOS’s total width can increase ESD robustness, but it should be aware of uniformity for ESD protection. In this thesis, ESD protection with LV p-type field-oxide devices (LVPFOD) in stacked configuration is proposed for HV applications in a 0.5-μm HV SOI process. For area and ESD robustness concerns, LV devices are proved with good ESD robustness per area. Stacking increases trigger voltage and holding voltage so that the devices meet the conditions. Therefore, stacking can be one of the best ways for ESD protection in HV applications. In ESD protection design for HV applications, holding voltage of a device is an important factor. When holding voltage of a device is lower than supply voltage, it is possible that latchup occurs in applications. Stacked LVPFOD with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications. In this thesis, the effect of the stacked ESD protection device’s resistance on Human Body Model (HBM) and Machine Model (MM) current waveform is studied. It is shown that the stacked device’s resistance can have a significant impact on the peak current and damping waveform, especially for MM ESD test. Because the load resistance of MM is dominated by stacked device and the HBM is dominated by 1.5 kΩ, the MM ESD level increases by the numbers of stacked LVPFOD, and all the HBM ESD level are the same.en_US
dc.language.isoen_USen_US
dc.subject靜電放電zh_TW
dc.subject絕緣層覆矽製程zh_TW
dc.subject高壓應用zh_TW
dc.subject人體放電模式zh_TW
dc.subject機器放電模式zh_TW
dc.subjectElectrostatic Discharge, ESDen_US
dc.subjectsilicon on insulator process, SOI processen_US
dc.subjectHugh-voltage applicationen_US
dc.subjectHuman-Body Model, HBMen_US
dc.subjectMachine Model, MMen_US
dc.title100至200伏特SOI製程高壓積體電路之靜電放電防護設計zh_TW
dc.titleOn-Chip ESD Protection Design for High-Voltage ICs in 100 ~ 200V SOI Processen_US
dc.typeThesisen_US
dc.contributor.department電子工程學系 電子研究所zh_TW
Appears in Collections:Thesis