標題: Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devices
作者: Li, Yiming
Hwang, Chih-Hong
Cheng, Hui-Wen
電信工程研究所
Institute of Communications Engineering
關鍵字: Threshold voltage fluctuation;Random dopant;Process-variation;Gate-length deviation;Line-edge roughness;Modeling and simulation
公開日期: 1-Mar-2009
摘要: Impact of the intrinsic fluctuations on device characteristics, such as the threshold voltage (V(th)) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced V(th) fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO(2) for the 1.2 and 0.8 nm EOTs, Al(2)O(3) for the 0.4 nm EOT and HfO(2) for the 0.2 nm EOT) are then for the first time compared with the results of 16 nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property, Result of this study confirms the suppression of V(th) fluctuations with the gate oxide thickness scaling (using high-kappa dielectric). It is found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device's scaling and have potential in the nanoelectronics application. (C) 2008 Elsevier B.V. All rights reserved.
URI: http://dx.doi.org/10.1016/j.mee.2008.02.013
http://hdl.handle.net/11536/12623
ISSN: 0167-9317
DOI: 10.1016/j.mee.2008.02.013
期刊: MICROELECTRONIC ENGINEERING
Volume: 86
Issue: 3
起始頁: 277
結束頁: 282
Appears in Collections:Conferences Paper


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