標題: Manufacturing performance evaluation for IC products
作者: Hsieh, KL
Tong, LI
工業工程與管理學系
Department of Industrial Engineering and Management
關鍵字: integrated circuit (IC);manufacturing performance;yield analysis;yield model
公開日期: 1-三月-2006
摘要: As we known, the product diversity and complexity in the production line will gradually increase. When the multiple products were alternately produced at the same line, the manufacturing performance will be difficult to evaluate. In particular, traditional process capability analysis and related process capability indexes cannot be directly employed to the IC manufacturing process. As we know, the yield has a direct effect on the manufacturing cost. Hence, yield is frequently used by most IC manufacturers to evaluate manufacturing performance. The diversity of function will become another analytic consideration due to that the component density, wafer area and product complexity of an IC product rapidly increase. Hence, the diversity of function can be regarded as the evaluated factor. Additionally, the defects on a wafer will begin to cluster as the wafer area gradually increases. Therefore, only using the yield to represent manufacturing performance may not lead to an appropriate judgment. In particular, only using the yield to evaluate the process's stability and the product's maturity can not provide a meaningful resolution. The primary reason is that the inherent features in the processes or products are not included into analyzing. For instance, even though the defect count, defect size and defect distribution are the same, the yield loss of the complicate manufactured product will be less than that of the simple manufactured product. In this study, we propose a simple performance evaluation index to assess the manufacturing performance in the IC manufacturing industry. This evaluation index is constructed according to a modified Poisson yield model, and the related parameters regarding the process or product (e.g., the minimum linewidth, the area of a die, the number of manufactured process or layer, the degree of defect clustering, and so on.) are taken into consideration. In addition, an integrated evaluation procedure is also suggested to evaluate the performance of the manufacturing of multiple IC products. According to the result obtained from the illustrative example, the index and the procedure can overcome the drawback of separately using yield or defect count in the analysis. The rationality and the feasibility of the proposed evaluated index and the procedure can be verified by demonstrating the illustrative example.
URI: http://dx.doi.org/10.1007/s00170-004-2382-2
http://hdl.handle.net/11536/12559
ISSN: 0268-3768
DOI: 10.1007/s00170-004-2382-2
期刊: INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY
Volume: 28
Issue: 5-6
起始頁: 610
結束頁: 617
顯示於類別:期刊論文


文件中的檔案:

  1. 000236497300024.pdf