標題: Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack
作者: Chung, SS
Yeh, CH
Feng, HJ
Lai, CS
Yang, JJ
Chen, CC
Jin, Y
Chen, SC
Liang, MS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: atomic layer deposition (ALD);gate stack;narrow-width effect;negative bias temperature instability (NBTI);shallow trench isolation (STI)
公開日期: 1-三月-2006
摘要: For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The ID degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which holetrap-induced V-T is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device ID degradation. In addition, the V-T rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N-2 content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.
URI: http://dx.doi.org/10.1109/TDMR.2006.871415
http://hdl.handle.net/11536/12521
ISSN: 1530-4388
DOI: 10.1109/TDMR.2006.871415
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 6
Issue: 1
起始頁: 95
結束頁: 101
顯示於類別:期刊論文


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  1. 000236944800014.pdf