Title: An Area-Efficient BCH Codec with Echelon Scheduling for NAND Flash Applications
Authors: Yang, Chi-Heng
Chen, Yi-Hsun
Chang, Hsie-Chia
Department of Electronics Engineering and Institute of Electronics
Issue Date: 1-Jan-2013
Abstract: This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite field divider is applied in the key equation solver. Moreover, by making use of the fact that the degree of error locator polynomial increases at most by 1 in each iteration, an echelon scheduling architecture with 6 finite field multipliers is presented. After implemented in UMC 1P9M 90 nm process, the proposed codec can achieve 385 MHz and 3.08 Gbit/s throughput with 147.8K gate-count from post-layout simulation results.
URI: http://hdl.handle.net/11536/125075
ISBN: 978-1-4673-3122-7
ISSN: 1550-3607
Begin Page: 4332
End Page: 4336
Appears in Collections:Conferences Paper