Title: A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
Authors: Liao, Wei-Nan
Lien, Nan-Chun
Chang, Chi-Shin
Chu, Li-Wei
Yang, Hao-I
Chuang, Ching-Te
Jou, Shyh-Jye
Hwang, Wei
Tu, Ming-Hsien
Huang, Huan-Shun
Wang, Jian-Hao
Kan, Paul-Sen
Hu, Yong-Jyun
Department of Electronics Engineering and Institute of Electronics
Issue Date: 1-Jan-2013
Abstract: This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive DataAware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 1.07GHz@1.2V and 887MHz@1.1V at 25 degrees C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25 degrees C.
URI: http://hdl.handle.net/11536/125067
ISBN: 978-1-4799-1166-0
ISSN: 2164-1676
Begin Page: 110
End Page: 115
Appears in Collections:Conferences Paper