Title: Discrete dopant fluctuated 20nm/15nm-gate planar CMOS
Authors: Yang, Fu-Liang
Hwang, Jiunn-Ren
Chen, Hung-Ming
Shen, Jeng-Jung
Yu, Shao-Ming
Li, Yiming
Tang, Denny D.
電信工程研究所
Institute of Communications Engineering
Issue Date: 2007
Abstract: We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V-t standard deviation up to 40mV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V-t variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.
URI: http://hdl.handle.net/11536/12501
http://dx.doi.org/10.1109/VLSIT.2007.4339695
ISBN: 978-4-900784-03-1
DOI: 10.1109/VLSIT.2007.4339695
Journal: 2007 Symposium on VLSI Technology, Digest of Technical Papers
Begin Page: 208
End Page: 209
Appears in Collections:Conferences Paper


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