Title: A 10Gb/s 44.2 dB Adaptive Equalizer with Duobinary Tracking Loop in 0.18 mu m CMOS
Authors: Chang, Po-Hsuan
Li, An-Siou
Tsai, Chia-Ming
Department of Electronics Engineering and Institute of Electronics
Keywords: Equalizer;Adaptive;Duobinary;offset cancellation;Decision Feedback Equalizer
Issue Date: 1-Jan-2014
Abstract: This paper presents an adaptive equalizer that converts the attenuated signal into Duobinary signaling scheme, combined with automatic Duobinary tracking technique to produce high quality Duobinary signal for simplifying the Duobinary decoding process and achieving higher data rate. The adaptive equalizer uses dual gain-mode topology that allows higher gain when the received signal is highly attenuated, and allows lower power consumption when the received signals pass through low-attenuation channel. A background offset cancellation loop circuit is added to increase the clock phase margin of the equalizer. The chip is fabricated in 0.18 mu m CMOS technology and operates at data rate of 10 Gb/s. The measurement results show that the equalizer recovers data properly for FR-4 trace with length ranging from 3 inches to 66 inches. The equalizer achieves clock phase margin of 58 % for 66-inch channel with BER less than 10(-12) and consumes power of 28.4 mW under high gain mode with 1.8V power supply.
URI: http://hdl.handle.net/11536/124906
ISBN: 978-1-4799-3432-4
ISSN: 0271-4302
Begin Page: 2133
End Page: 2136
Appears in Collections:Conferences Paper