標題: A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step
作者: Lai, Wei-Ting
Yang, Kuo-Ching
Hsu, Ting-Chia
Liao, Po-Hsiang
George, Thomas
Li, Pei-Wen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Gate-stacking heterostructure;SiGe channel;Self-aligned;Ge quantum dot
公開日期: 19-May-2015
摘要: We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 x 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.
URI: http://dx.doi.org/10.1186/s11671-015-0927-y
http://hdl.handle.net/11536/124805
ISSN: 1556-276X
DOI: 10.1186/s11671-015-0927-y
期刊: NANOSCALE RESEARCH LETTERS
Volume: 10
起始頁: 0
結束頁: 0
Appears in Collections:Articles


Files in This Item:

  1. 9c802418df0b5198f4f675728177557a.pdf