|標題:||Demystifying Iddq Data With Process Variation for Automatic Chip Classification|
|作者:||Chang, Chia-Ling (Lynn)|
Wen, Charles H. -P.
Undergraduate Honors Program of Electrical Engineering and Computer Science
|關鍵字:||Circuit testing;data mining;Iddq|
|摘要:||Iddq testing is an integral component of test suites for the screening of unreliable devices. As the scale of silicon technology continues shrinking, Iddq values and associated fluctuations increase. In addition, increased design complexity makes defect-induced leakage currents difficult to differentiate from full-chip currents. Consequently, traditional Iddq methods result in more test escapes and yield loss. This brief proposes a new test method, called s-Iddq to provide the following: 1) Iddq analysis with process-parameter deduction and 2) the algorithm for automatic chip-classification called collective analysis without the need to manually determine threshold values. We randomly inserted a number of multiple defects into samples of ISCAS\' 89 and IWSL\'05 benchmark circuits. Experimental results demonstrate that the proposed s-Iddq method can achieve higher classification accuracy than single-threshold Iddq testing or sigma-Iddq in a 45-nm technology. The overall classification accuracy of the collective analysis achieve averaged 99.28% and 99.70% on s-Iddq data from process-parameter deductions with average-case search and multilevel search, respectively, demonstrating that the influence of process variation and design scaling can be significantly reduced to enable a better identification of defective chips.|
|期刊:||IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS|
|Appears in Collections:||Articles|